This list does not contain any of the order-only prerequisites for those see the ‘ $|’ variable, below. So if you list a prerequisite more than once for a target, the value of $^ contains just one copy of the name. A target has only one prerequisite on each other file it depends on, no matter how many times each file is listed as a prerequisite.
For prerequisites which are archive members, only the named member is used. The names of all the prerequisites, with spaces between them. For prerequisites which are archive members, only the named member is used The names of all the prerequisites that are newer than the target, with spaces between them. If the target got its recipe from an implicit rule, this will be the first prerequisite added by the implicit rule. ‘ $%’ is empty when the target is not an archive member. For example, if the target is foo.a(bar.o) then ‘ $%’ is bar.o and ‘ is foo.a. The target member name, when the target is an archive member. In a pattern rule that has multiple targets, ‘ is the name of whichever target caused the rule’s recipe to be run. If the target is an archive member, then ‘ is the name of the archive file. A common mistake is attempting to use within the prerequisites list this will not work.Īutomatic file name of the target of the rule. they cannot be accessed directly within the prerequisite list of a rule.only have values within the recipe - you cannot use them anywhere within the target list of a rule (they have no value there and will expand to the empty string).For example, you would use ‘ for the object file name and ‘ $<’ for the source file name. What you do is use another feature of make namely automatic variables, which are computed afresh for each rule that is executed, based on the target and prerequisites of the rule. o’ file: how do you write the ‘ cc’ command so that it operates on the right source file name? You cannot write the name in the recipe, because the name is different each time the implicit rule is applied. Suppose you are writing a pattern rule to compile a ‘. The rules are the commands needed to make the target.Ī simple makefile might be structured like this:
The dependencies are source code or other things needed to make the target. The target is normally either an executable or object file name. StructureĪ makefile consists of three sections: target, dependencies, and rules. If you call it something else you will have to use make -f to call it. You can, however, give the file any name. You can then just invoke make and it will follow these instructions. Usually, the file that contains all the commands to make is called makefile or Makefile. You no longer have to write long and complex compiler commands every time. This is handled by the program make, following the commands in your makefile - it will only recompile the files which contains changes, and also makes it easier and faster to give the order to compile everything. If you then make a change to one of the files, you will have to recompile all the files. One will often have a program which have, say, several header files and a number of C source files. The purpose of makefiles is to help you with your coding projects.